1. Field of the Invention
The present invention relates to digital circuits and, more specifically, to a circuit that controls multiple clocking signals to reduce electromagnetic interference.
2. Description of the Prior Art
The peripheral component interconnect (PCI) standard specifies a computer bus for attaching peripheral devices to a computer motherboard. These devices can take the form of integrated circuits fitted onto the motherboard itself (called planar devices in the PCI specification) or expansion cards that fit in sockets. The PCI bus is common in modern PCs, but it also appears in many other computer types. The PCI specification covers the physical size of the bus (including wire spacing), electrical characteristics, bus timing, and protocols.
Most digital circuits employ some sort of clocking circuit to generate a series of clock pulses that activate latches throughout the circuit. When a clock pulse is asserted, a latch is enabled to acquire and store a data value from a logic unit. By asserting clock pulses periodically, data values are able to propagate through the circuit in an orderly manner, thereby ensuring that any given data unit is correctly paired with a corresponding data unit at the beginning of a logical operation.
More complex digital circuits often employ several different clocks, sometimes operating at different frequencies. Also, in some circuits many latches may need to be activated simultaneously, but a single clock circuit may lack sufficient power to drive all of the latches. Therefore, it is common to regenerate clock signals through the use of a “clock tree.” Essentially, a clock tree includes a plurality of drivers that receive a clock signal and replicate it with power restored to the original level, to several different clock signal lines.
Some clock signals are received by circuits that employ phase locked loops (PLLs) that sense when a given clock pulse is slightly out of phase with sequential pulses in a clock signal and correct a pulse when such an out of phase relationship is detected. Thus, a slight delay in a received clock pulse will not interfere with the normal timing of operations in a synchronous circuit.
Each clock signal generates some electromagnetic radiation when being asserted. Typically, this electromagnetic radiation is insignificant in simple circuits, but in more complex circuits it is referred to as electromagnetic interference (EMI). When several different clock signals are asserted coherently, the combined EMI from the clock signals can be enough to interfere with the normal operation of the circuit. This problem may be especially critical in high density circuits, such as those employed in PCI applications.
In a representative timing diagram 10 of a prior art system, shown in FIG. 1, (showing only relative amounts and not corresponding to any actual units of measurement) a first clock signal 12, a second clock signal 14 and a third clock signal 16 each include a plurality of periodic transitions, such a rising edges and falling edges. An indication of EMI level 20 demonstrates that when transitions of two of the clock signals are substantially aligned, then the EMI level 20 increases and when transitions of all three clock signals are aligned, then the EMI level 20 is at its maximum.
Multiple clock signals in a complex circuit can generate EMI spikes that can have a severe disruptive effect on various parts of the circuit. Because the EMI effect occurs in a transient manner (only when several signals are in alignment), the effect of the EMI spikes can be particularly hard to debug.
EMI is not only a concern for interoperability but it is also limited by regulatory agencies. For example, FCC regulations limit the amount of EMI that may be given off by a machine. Also, CISPR country requirements limit EMI in order to ship machines to member countries. While a machine might be perfectly operable, it cannot be sold if its EMI level exceeds regulatory limits.
Therefore, there is a need for a system that reduces electromagnetic interference in a circuit due to coherent clock pulses from different clock signals.